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AVR UC3 FLASH MICROCONTROLLERS
Everywhere You Are ?
System Performance
For embedded systems, system performance is much more than a good MIPS number. It is important to
have powerful, fast peripherals and an energy-efficient memory system that allows the application to run
effortlessly with minimal power consumption.
Single Cycle SRAM
Fast SRAM access is critical to achieving the
necessary computing performance. The UC3 CPU
has a single-cycle access to the SRAM embedded
in the CPU itself.
Split Memory Architecture with
DMA
High performance peripheral modules require
a true memory DMA controller. In addition, the
memory is partitioned such that one memory block
resides inside the CPU to support single cycle
memory access during program execution. To maximize the bandwidth, two more SRAMs are placed on
two different layers on the multi-layered high-speed bus and can act as data buffers for high-speed periph-
erals like the USB. The SRAMs are coupled to the memory DMA controller such that data can be efficiently
moved without loading the CPU.
Bus Matrix
To ensure sufficient data bandwidth, the 32-bit AVR architects have designed a set of parallel buses where
each bus master has a dedicated bus for all the slaves. This gives the 32-bit AVR a tremendous data band-
width and removes the bottleneck encountered in traditional 32-bit microcontrollers.
Unrivalled DSP Performance
By including powerful instructions for single cycle multiply
accumulate and fractional multiply for various number
formats, the 32-bit AVR UC3 delivers unrivalled DSP per-
formance compared to legacy architectures. In the AVR
UC3 Software Framework more than 70 DSP functions
have been assembly optimized utilizing these instruc-
tions. DSP has never been easier.
Code Density and Efficiency
The 32-bit AVR architecture was designed in close cooperation with compiler experts. This ensures that the
AVR architecture excels when compiling high-level programming languages like C and C++. Compact and
extended instructions are chosen by the compiler without any performance penalty introduced by legacy
architectures. A compact code is important, not only because it resolves in a smaller memory footprint, but
also because a dense instruction can easily be optimized for both speed and size.
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